Browse Prior Art Database

Automatic Pulse Width Control

IP.com Disclosure Number: IPCOM000096840D
Original Publication Date: 1963-Dec-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Wood, BG: AUTHOR [+2]

Abstract

This circuit controls the pulse width output of a trigger circuit by automatically adjusting its biasing threshold. An analog input signal is fed through peak storage network 10. This stores the peak amplitude of the signal as a DC level. This DC level is then applied to trigger 11 to set the biasing threshold. This occurs at the time the signal, which caused the DC level, is applied to trigger 11 by way of delay 12. The condition is realized by delaying the input signal in delay 12 before applying it to the input to trigger 11 by the length of time required to generate the peak DC level from network 10.

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Automatic Pulse Width Control

This circuit controls the pulse width output of a trigger circuit by automatically adjusting its biasing threshold. An analog input signal is fed through peak storage network 10. This stores the peak amplitude of the signal as a DC level. This DC level is then applied to trigger 11 to set the biasing threshold. This occurs at the time the signal, which caused the DC level, is applied to trigger 11 by way of delay 12. The condition is realized by delaying the input signal in delay 12 before applying it to the input to trigger 11 by the length of time required to generate the peak DC level from network 10.

The trigger threshold control comprises transistor t1 which is biased on by the current through R1, and set by voltage divider R4 when no signal is present. Without the peak DC level input through R2, the biasing threshold of the trigger is reached when the voltage on the base of T1 due to a positive signal voltage exceeds the magnitude of the voltage developed on the base of T1 through network R4. When the peak DC level input is included in the summing point on the base of T1, the biasing threshold is determined by the positive signal voltage, the negative voltage from divider R4, and the negative voltage generated by network 10.

Large signal voltages cause a more negative DC voltage to be applied to the trigger from network 10 than when smaller signal voltages are present. Thus, the amount of DC voltage supplied can be set through...