Browse Prior Art Database

Execution Control Checking

IP.com Disclosure Number: IPCOM000096854D
Original Publication Date: 1963-Dec-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 43K

Publishing Venue

IBM

Related People

Wolff, CH: AUTHOR

Abstract

This apparatus checks the controls of a synchronous computer. In a computer, the controls are governed by a set of control latches. These have a particular status at any particular time during a sequence of computer operations. An arrangement of control latches is shown. Included are a fixed portion 10 containing the instruction code and modifiers, a predetermined portion 12 containing the micro-program for the particular instruction. Also, there is a variable portion 14 which has an initial condition that can change status in response to a change in the data acted upon.

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Execution Control Checking

This apparatus checks the controls of a synchronous computer. In a computer, the controls are governed by a set of control latches. These have a particular status at any particular time during a sequence of computer operations. An arrangement of control latches is shown. Included are a fixed portion 10 containing the instruction code and modifiers, a predetermined portion 12 containing the micro-program for the particular instruction. Also, there is a variable portion 14 which has an initial condition that can change status in response to a change in the data acted upon.

the parity of the control latches can be predicted for any set of instructions. This is since the contents of the variable portion 14 for an instruction always has a known initial condition. These precomputed parities are regenerated in predetermined parity sequence generator 16. Output 18 of generator 16 provides a series of 1's and 0's. These, at successive times in the machine cycle, correspond to the parity of the control latches at that time. During machine operation the variable portion 14 can change in response to changes in the data acted upon. Devices are provided for updating parity sequence 18 to reflect the changed condition of the variable latches.

For example, the instruction can call for a test to be made upon the data being processed.

This test is performed by computer logic 20. In response to this test, one variable latch 14 is changed to its opposite s...