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Delay Pulse Generator

IP.com Disclosure Number: IPCOM000096894D
Original Publication Date: 1962-Jan-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 3 page(s) / 44K

Publishing Venue

IBM

Related People

Stevenson, DA: AUTHOR [+2]

Abstract

This pulse generator has adjustable output pulses over a limited range, interlocked between the pulses and a clock length of less than twice the delay line period.

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Delay Pulse Generator

This pulse generator has adjustable output pulses over a limited range, interlocked between the pulses and a clock length of less than twice the delay line period.

Included in the pulse generator is latch circuit 20 comprising interconnected AND INVERT's 22 and 24. The output from 20 is supplied through driver 28 to a first tapped delay line 26 of pulse period T/4. The output from delay 26 is taken across load resistor 30. Driver 28 and resistor 30 have an impedance which matches the characteristic impedance of delay 26. The output from delay 26 is supplied through inverter 34 and driver 36 to second tapped delay line 32 of pulse period T/4. The output from delay 32 is taken across load resistor 38. It is inverted with respect to the output appearing across resistor 30 due to inverter
34. Driver 36 and resistor 38 match the characteristic impedance of delay 32. The output from delay 32 also returns to the latch 20 for resetting. Input signals to the generator are applied to terminal 40.

The generator has two output signals, developed from logic circuits receiving inputs from the tapped delay lines. One circuit comprises AND 42 having an input from each of the tapped delay lines and an output supplied to emitter follower 44. The second circuit comprises OR 46 having an input from each of the tapped delay lines and an output supplied to inverter 50 through emitter follower 48.

The operation of the generator is traced in connection with the timing diagram which has four equal pulse periods totaling T. Each pulse period is equal to the delay period of the tapped delay lines. The timing diagram indicates circuit conditions at points A through G, these points being designated in the circuit.

Normally, the input, indicated at A, is up. However, the input to delay 26, indicated by B, is down due to the inverting action of latch 20. Correspondingly, the output from delay 26, indicated by C, is down. The input to delay 32, indicated by D, is up, however, due to inverter 34. Similarly, the output from delay 32 and the reset to latch 20, indicated by E, is up. The output from the first logic block, indicated by F, is down since the inputs are unlike. The output from the second logic block, indicated by C, is also down due to inverter 50, which converts the unlike signals to OR 46 to a down signal.

When the input signal level is momentarily lowered to produce pulse...