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Gated Clock Distribution System

IP.com Disclosure Number: IPCOM000096895D
Original Publication Date: 1962-Jan-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Related People

Nestork, WJ: AUTHOR

Abstract

In general, three distinct problems arise in the design of circuitry for distribution of various clock pulses of a large data processing system. When more than one clock pulse is used, it is necessary these various pulses have a definite relationship to one another as to their time reference base. These clock pulse lines are very often required to drive hundreds or even thousands of logical loads. This poses a problem of powering, especially at higher clock frequencies in the megacycle region. The skew and delays associated in referencing one clock pulse to another and in propagating the pulse through a number of power drivers shrinks and extends the basic oscillator pulse. This very often reduces the repetition rate at which a given machine can operate.

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Gated Clock Distribution System

In general, three distinct problems arise in the design of circuitry for distribution of various clock pulses of a large data processing system. When more than one clock pulse is used, it is necessary these various pulses have a definite relationship to one another as to their time reference base.

These clock pulse lines are very often required to drive hundreds or even thousands of logical loads. This poses a problem of powering, especially at higher clock frequencies in the megacycle region. The skew and delays associated in referencing one clock pulse to another and in propagating the pulse through a number of power drivers shrinks and extends the basic oscillator pulse. This very often reduces the repetition rate at which a given machine can operate.

This clock pulse reference and distribution system minimizes these three problems. The system provides for four clock pulses, X, X bar, Y and Y bar. The logical layout of the machine requires that the X clock pulse not achieve its 1 level before the Y pulse achieves its 0 level. Also, the Y pulse cannot achieve its 1 level before the X pulse achieves its 0 level.

The output of oscillator 10, the source of X1 pulses, is fed to an inverter 12 to produce Y1 pulses which are 180 degrees out of phase with the X1 pulses. The X1 pulses are fed through -AND inverter 14 when they are conditioned by Y type pulses. The Y1 pulses are fed through -AND inverter 16 when conditioned by X pulses. T...