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Priority Scanning Selection Of Address Register

IP.com Disclosure Number: IPCOM000096898D
Original Publication Date: 1962-Jan-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 54K

Publishing Venue

IBM

Related People

Crawford, JK: AUTHOR

Abstract

This is a priority circuit for random time multiplexing a connection between an output bus (not shown) and one of a plurality of asynchronous I/O sources (not shown). Also, the gates for connecting the respective I/O devices to the bus are not shown. Each I/O source makes available a byte of data in its output register for a short period of time until its next byte is read. A byte is a simultaneous group of data bits. The circuit controls the order of connection of respective 1/0 output registers to the common bus. Thus, I/O output data is transmitted to an ultimate receiving source without confusion and quickly enough so that each I/O register is cleared before the I/O can set its next byte of data into its register.

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Priority Scanning Selection Of Address Register

This is a priority circuit for random time multiplexing a connection between an output bus (not shown) and one of a plurality of asynchronous I/O sources (not shown). Also, the gates for connecting the respective I/O devices to the bus are not shown. Each I/O source makes available a byte of data in its output register for a short period of time until its next byte is read. A byte is a simultaneous group of data bits. The circuit controls the order of connection of respective 1/0 output registers to the common bus. Thus, I/O output data is transmitted to an ultimate receiving source without confusion and quickly enough so that each I/O register is cleared before the I/O can set its next byte of data into its register. The I/O devices are arranged so that I/O 1 has the highest output priority in a priority sequence, followed by I/O 2, I/O 3, and I/O 4 which has the lowest priority output.

Triggers T1... T4 prevent an I/O device from obtaining access to the bus more than once per service request SR. When an SR is not being made, any I/O SR line disarms its AND and maintains a reset input to its associated trigger T1... T4 so that it cannot be set. In this state, the trigger output conditions its AND, which nevertheless remains deconditioned by no SR input. When the SR line is brought up, it conditions its AND to provide an output, if none of its other inputs is deconditioned by feedback from another priority trigger T10... T13, if on. The AND output sets its associated trigger T10... T13, if no other trigger in that group is set. An I/O clock pulse arrives shortly after the SR line is brought up and sets its trigger T1... T4 to cause the trigger output to decondition its AND and stop its output pulse. No further output from the AND occurs until its next SR. In additi...