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Browse Prior Art Database

High Speed Logic Circuit

IP.com Disclosure Number: IPCOM000096902D
Original Publication Date: 1962-Jan-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 28K

Publishing Venue

IBM

Related People

Nestork, WJ: AUTHOR

Abstract

The transistor logic circuit comprises an emitter follower and an inverter coupled so that the emitter follower drives the inverter. Its speed is enhanced if a capacitive device is connected in circuit with the two transistors to provide a spike pulse to the inverter, when it is activated.

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High Speed Logic Circuit

The transistor logic circuit comprises an emitter follower and an inverter coupled so that the emitter follower drives the inverter. Its speed is enhanced if a capacitive device is connected in circuit with the two transistors to provide a spike pulse to the inverter, when it is activated.

Transistor T1 is the emitter follower and transistor T2 is the inverter. It is connected to receive the T1 output at its base electrode, coupled through resistor R1 and diode D1. The capacitor C1 connects to bridge R1 and D1 between the T1 output and the T2 input.

Under normal conditions, when the input signal level at point A is negative, T1 and T2 are nonconductive. Conduction of T2 is prevented during this mode of operation by the forward biasing of D1 by means of supplies +V1 and -V. This permits current to flow through the resistors R2, R3 and D1 to the current sink comprising R4 and -V. Thus, the level of the output signal is clamped by diode D2, connected to the +V2 voltage supply, to a level approximating +V1. Similarly, the level of the T1 output is clamped by diode D3, connected to the +V3 voltage supply.

As a positive shift occurs at A, it is propagated without significant attenuation to the point B. Transistor T1 operates to provide current amplification. This rise is also carried to point C, causing D1 to be back biased. This enables T2 to be activated as base current is supplied through R3. As T2 turns on, the level of output D begins to f...