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Gated Pulse Generator

IP.com Disclosure Number: IPCOM000096904D
Original Publication Date: 1962-Jan-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 29K

Publishing Venue

IBM

Related People

Soychak, FJ: AUTHOR

Abstract

In this gated pulse generator circuit, a positive pulse applied to either A or B renders the circuit quiescent. Similarly, the application of a negative pulse to the gate 1 or a positive pulse to the gate 2 terminal renders the circuit quiescent. Removal of these gate pulses renders the circuit operative. For example, the removal of a positive pulse from either A or B restores the input to transistor 10 at ground and 10 is turned off.

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Gated Pulse Generator

In this gated pulse generator circuit, a positive pulse applied to either A or B renders the circuit quiescent. Similarly, the application of a negative pulse to the gate 1 or a positive pulse to the gate 2 terminal renders the circuit quiescent. Removal of these gate pulses renders the circuit operative. For example, the removal of a positive pulse from either A or B restores the input to transistor 10 at ground and 10 is turned off.

The output 1 becomes +12 volts and turns off transistor 11. Consequently, output 2 becomes -12 volts and turns off transistor 12. The output 3 then becomes +12 volts and transistor 10 turns on, causing transistor 11 to turn on. Then, transistor 12 turns on to cause transistor 10 to turn off. Thus, there is provided a pulse generator circuit with the output pulses timed by the inherent delay characteristics of the circuit components. It is rendered quiescent through the application of control gate pulses.

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