Browse Prior Art Database

Time Shared Parity Circuitry

IP.com Disclosure Number: IPCOM000096934D
Original Publication Date: 1962-Feb-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 3 page(s) / 56K

Publishing Venue

IBM

Related People

Card, MJ: AUTHOR [+2]

Abstract

The apparatus shares the use of various groups of parity determining P circuits I of the type described on page 20 of IBM Technical Disclosure Bulletin, Volume 3, No. 8, January 1961. These P circuits are used collectively to determine the parity of all bits in register 2. This operation is carried out during the broadside transfer of bits of an entire word between register 2 and external apparatus, not shown, over lines 26A and 26B. The P circuits are used individually to determine the parity of bits in the individual byte positions of register 2 to which the P circuits are assigned. This operation is carried out during the transfer of bits by byte between each of the various byte positions of register 2 and I/O gating device 20 over lines 27A and 27B.

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Time Shared Parity Circuitry

The apparatus shares the use of various groups of parity determining P circuits I of the type described on page 20 of IBM Technical Disclosure Bulletin, Volume 3, No. 8, January 1961. These P circuits are used collectively to determine the parity of all bits in register 2. This operation is carried out during the broadside transfer of bits of an entire word between register 2 and external apparatus, not shown, over lines 26A and 26B. The P circuits are used individually to determine the parity of bits in the individual byte positions of register 2 to which the P circuits are assigned. This operation is carried out during the transfer of bits by byte between each of the various byte positions of register 2 and I/O gating device 20 over lines 27A and 27B. Each P circuit 1 has level (parity) inputs connected to a particular byte group of register 2 outputs. Each P circuit has even E and odd O sampling inputs, energized after the level inputs are applied to them. Device 20 and the external apparatus are assumed to use odd parity.

The input and outputs of adjacent P circuits 1 are connected by gates 3. With all gates 3 conditioned, a signal applied to either 0 input 9D or E input 24A generates a parity signal at one of outputs 5 for all bits then stored within register
2. Similarly, when gates 3 are deconditioned and a sample pulse is applied to an E input of any one of circuits 1 over a conductor such as 24A, an even parity signal for the bits stored in a particular byte position of register 2 is delivered. This is effected through OR 6 for distribution via gates 7 and 8 and may be used during the transfer of bits between device 20 and register 2.

In accordance with the transfer to be currently effected, read and write command generators 12 and 13, respectively, furnish: levels for conditioning gates 7 and 8A, sample pulses via OR 14 to the sample input of ring counter 16, stepping pulses to counter 16 via OR 15, and other pulses and levels.

When a broadside exchange between register 2 and external apparatus is effected, counter 16 is set so that only flip-flop 17C is in I state. Consequently, all gates 3 are conditioned via conductors 19A, 19B, etc. When a sample pulse from either generator 12 or 13 is delivered via OR 15A and conductor 31A, the conditioned output gate of counter 16 gates a sample pulse on conductor 9. This ripples through all P circuits 1 to generate an appropriate output on one of conductors 5.

In reading a byte from device 20 to register 2, an appropriate level is placed on read conductor 33. This causes device 20 to transfer recorded data bits and a parity bit...