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Ring Checking

IP.com Disclosure Number: IPCOM000096935D
Original Publication Date: 1962-Feb-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 37K

Publishing Venue

IBM

Related People

O'Connor, LT: AUTHOR

Abstract

Some direct coupled rings have adjacent triggers overlappingly set during ring progression from one stage to the next. The circuitry includes a pair of OR's 10 and 11. OR 10 receives inputs from odd numbered triggers in the ring. OR 11 receives inputs from even numbered triggers in the ring. The outputs of the OR's are applied to AND's 12 and 13. Inverter 14 causes outputs from AND 12 to be inverted with respect to each of them. Sampling timing pulses A and B are provided. An A sample pulse occurs during each progression overlap. A B sample pulse occurs between progression overlaps. A pair of AND's 16 and 17 respectively receives A and B sample pulses. They also receive the inverted and non-inverted output of AND's 12 and 13, respectively.

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Ring Checking

Some direct coupled rings have adjacent triggers overlappingly set during ring progression from one stage to the next. The circuitry includes a pair of OR's 10 and 11. OR 10 receives inputs from odd numbered triggers in the ring. OR 11 receives inputs from even numbered triggers in the ring. The outputs of the OR's are applied to AND's 12 and 13. Inverter 14 causes outputs from AND 12 to be inverted with respect to each of them. Sampling timing pulses A and B are provided. An A sample pulse occurs during each progression overlap. A B sample pulse occurs between progression overlaps. A pair of AND's 16 and 17 respectively receives A and B sample pulses. They also receive the inverted and non-inverted output of AND's 12 and 13, respectively. The outputs of AND's 16 and 17 provide an A or a B sample pulse, when an overlap condition of the ring is improper, to indicate an error. The pulse is used to set an error-registering circuit
18.

In view of the fact that the pulses are supplied to AND 16 in an inverted condition, AND 16 supplies no output under normal operation. In AND 17, on the other hand, the B sample pulses do not occur simultaneously with the priming of AND 17 by the output from AND 13. No output from AND 17 under proper operation results.

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