Browse Prior Art Database

Asynchronous Computer Control

IP.com Disclosure Number: IPCOM000096937D
Original Publication Date: 1962-Feb-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 3 page(s) / 71K

Publishing Venue

IBM

Related People

Meade, RM: AUTHOR

Abstract

This control circuit asynchronously regulates information flow in a computer. It responds to selection signals for alternative routing of the information flow in the computer. The control circuit also minimizes the circuit timing delay by simplified logic.

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Asynchronous Computer Control

This control circuit asynchronously regulates information flow in a computer. It responds to selection signals for alternative routing of the information flow in the computer. The control circuit also minimizes the circuit timing delay by simplified logic.

Information flow in an asynchronous computer is depicted (upper drawing) by a serial arrangement of registers (R) 20 and logic circuitry (L) 22 having gates 24 at their inputs and outputs. Each gate 24 is regulated by a control circuit (C) 28. Upstream information from prior C circuits is supplied on lines 29 to reset the C circuits. Downstream information from subsequent C circuits is supplied on lines 31 to enable the C circuits. Additionally, a selection signal is supplied on line 33 to each C circuit. The absence of a selection signal causes the data from the L blocks to be routed to corresponding R's in another information channel. Finally, each control C receives a completion signal on lines 35 from the next upstream L stage. The completion signal indicates when the stage has completed the required logic process.

The details of a C circuit are shown in the middle drawing.

Each includes a pair of AND's 30 and 32. Both receive downstream enable signal 31, upstream completion signal 35, selection signal 33. Each has a line 37 for receiving timing signals from a pulse generator, and receives the upstream reset signal 29. The outputs from AND 30 are supplied to drivers 34 for turning on the gates. The three blocks, 49 provide signal level conversion between interconnected logic blocks.

A timing signal developed in the control circuit turns off AND's 30 and 32 which de-energize drivers 34. The signal is developed from the AND 32 output. This is supplied through signal level convert block 38, delay line 42 and, afterwards on line 37, returned to AND's 30 and 32. When AND 32 turns on, the circuit, comprising block 38, delay line 42 and AND 32, latches for a period determined by delay line 42. The timing signal along with the reset signal 29 is supplied to AND 44. This is connected to AND's 30 and 32 through delay line 48. The circuit, comprising AND 44, AND's 30 and 32 and delay line 48, form a trigger that insures AND's 30 and 32 are set to op...