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Transistor-Esaki Diode Shift Register

IP.com Disclosure Number: IPCOM000096945D
Original Publication Date: 1962-Feb-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 46K

Publishing Venue

IBM

Related People

Fisher, RC: AUTHOR

Abstract

The upper circuit is a basic storage element utilized in the three-stage shift register circuit (middle). The Esaki diode is biased through resistor Rb by the voltage - Vb such that it has two stable voltage states. One is a low voltage state which is below the base-emitter threshold voltage necessary to maintain transistor Q in conduction. The other is its high voltage state, which is above the base-emitter threshold voltage of Q so as to maintain it in conduction. Thus, the state of the storage element formed by Q and the Esaki diode is determined by the state of the Latter.

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Transistor-Esaki Diode Shift Register

The upper circuit is a basic storage element utilized in the three-stage shift register circuit (middle). The Esaki diode is biased through resistor Rb by the voltage - Vb such that it has two stable voltage states. One is a low voltage state which is below the base-emitter threshold voltage necessary to maintain transistor Q in conduction. The other is its high voltage state, which is above the base-emitter threshold voltage of Q so as to maintain it in conduction. Thus, the state of the storage element formed by Q and the Esaki diode is determined by the state of the Latter.

The waveform timing chart shows 1 is defined as a ground level and 0 as -10 volts. Assume initially that all transistors are off. Assume further that a 0 occurs on the data input at shift pulse time, t = 0. The shift pulse pair causes D2, D4 and D6 to be reversely biased and D1, D3 and D5 to be forwardly biased. When D1 conducts and the voltage at point X1 rises instantaneously to -5 volts, capacitor C1 cannot change its charge instantaneously. A reversely biasing positive pulse is applied to Esaki diode T1 so as to hold it in its low voltage state. Transistor Q1 remains in nonconduction. Transistors Q2 and Q3 remain in nonconduction as a result of similar biasing at points X1 and X2. At time t = 1, a 1 voltage level is applied to the input. D2 is forwardly biased and D1 is reversely biased. This causes a negative voltage pulse to appear at point X1. Th...