Browse Prior Art Database

Load Sharing Matrix Switch

IP.com Disclosure Number: IPCOM000096958D
Original Publication Date: 1962-Feb-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 29K

Publishing Venue

IBM

Related People

Ordemann, FA: AUTHOR [+2]

Abstract

Certain magnetic memory systems, e. g., word organized memories, require read and write drive currents of different magnitudes. This matrix switch produces sequential read and write drives which are unequal.

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Load Sharing Matrix Switch

Certain magnetic memory systems, e. g., word organized memories, require read and write drive currents of different magnitudes. This matrix switch produces sequential read and write drives which are unequal.

Part of the matrix switch is shown. Two cores are provided for each output, one to supply read drive and one to supply write drive. A common set of drive lines (only two appear) are coupled to the cores in load sharing arrangement. The windings on both cores are arranged as shown by the polarity dots. When the write drive line is energized, secondary circuit 1 on core 2 provides a write current of a certain magnitude. At the same time, secondary circuit 1 on core 1 acts as a dummy load. Such provides a closed circuit for current flow by means of the diode. Thus, a proper load R1 is present on core 1 to assure proper resetting. When the read drive line is energized, secondary circuit 2 on core 1 provides a read current. Core 2 is reset similarly to the write operation. That is, secondary circuit 2 on core 2 contains a diode to allow current to flow in one direction only. It also contains a resistor R2 which serves as a load on core 2 to assure proper resetting.

To provide the unequal read and write currents, the turns ratios on cores 1 and 2 are properly chosen. Also, the values of resistors R1 and R2 are individually adjusted for proper resetting of the cores.

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