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Modified Carry Completion Recognition Adder

IP.com Disclosure Number: IPCOM000096981D
Original Publication Date: 1962-Mar-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 26K

Publishing Venue

IBM

Related People

Gilchrist, B: AUTHOR

Abstract

Existing carry completion recognition adders use a carry completion recognition gate with as many entries as there are stages in the adder. The drawing shows the logic for the carry generation part of a carry completion recognition adder which has only one-half the number (n/2) of entries to the carry completion recognition gate as there are adder stages (n). This gives an average maximum carry sequence very little longer than that for existing carry completion recognition adders.

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Modified Carry Completion Recognition Adder

Existing carry completion recognition adders use a carry completion recognition gate with as many entries as there are stages in the adder. The drawing shows the logic for the carry generation part of a carry completion recognition adder which has only one-half the number (n/2) of entries to the carry completion recognition gate as there are adder stages (n). This gives an average maximum carry sequence very little longer than that for existing carry completion recognition adders.

The delay section of the adder is set equal to or slightly greater than the propagation time of a carry between two successive stages of the adder. The end stage adder has the same carry logic as Figure 5 of a publication by B. Gilchrist, JH Pomerene and SY Wong appearing in the IRE PGEC, December 1955 entitled Fast Carry Logic for Digital Computers with the exception of the number of entries to the carry completion gate.

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