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Epitaxially Diffused Transistor Fabrication

IP.com Disclosure Number: IPCOM000096992D
Original Publication Date: 1962-Mar-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 69K

Publishing Venue

IBM

Related People

van Ligten, RH: AUTHOR

Abstract

A plurality of epitaxially diffused transistors, such as NPN devices having their collectors electrically isolated from each other, is made on a single semiconductor wafer. The various fabrication steps bear letters related to those in the drawing.

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Epitaxially Diffused Transistor Fabrication

A plurality of epitaxially diffused transistors, such as NPN devices having their collectors electrically isolated from each other, is made on a single semiconductor wafer. The various fabrication steps bear letters related to those in the drawing.

The starting wafer (A) is a polished, high resistivity P-type silicon starting wafer. Selected surface areas (B) of the wafer are given an oxide coating 10.

A suitable donor impurity (C) is diffused through the holes in the oxide coating 10 by familiar procedures to establish the N+ regions. The diffusion conditions are adjusted to provide a low sheet resistance for the diffused regions. This is achieved by a high surface concentration of impurities.

The oxide coating 10 (D) is removed and then a thin epitaxial layer 11 is grown on the wafer. This layer is doped with a donor impurity to the level desired for the collector regions of the transistors. Selected surface areas (E) of the wafer are given an oxide coating 12.

An acceptor impurity (F) is diffused through the openings in the coating 12 to such a depth that the P-type region now extends to the surface of the wafer. The oxide coating 12 is removed. At this stage in the process, a plurality of N-type and N+type regions are present in the P-type wafer. These regions have a low sheet resistance because of the underlying highly-doped N+ material. However, the Ntype surface regions have the desired doping for the collector r...