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Asynchronous Binary Adder

IP.com Disclosure Number: IPCOM000096996D
Original Publication Date: 1962-Mar-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 54K

Publishing Venue

IBM

Related People

Hellerman, H: AUTHOR

Abstract

This adder operates upon the following principles: 1. Carries begin to propagate where the operand bits in a particular stage are both 1; 2. A carry, which is propagating from a lower order to a higher order terminates at a bit position, where both the operand bits are either 0 or at a bit position where both the operand bits are 1; 3. When a carry, which has propagated from a lower order, terminates at a particular bit position, the sum digit of the position where the carry terminates is a 1; 4. When the number of carries which have terminated equals the number of carries which have started, the addition is complete.

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Asynchronous Binary Adder

This adder operates upon the following principles: 1. Carries begin to propagate where the operand bits in a particular stage are both 1; 2. A carry, which is propagating from a lower order to a higher order terminates at a bit position, where both the operand bits are either 0 or at a bit position where both the operand bits are 1; 3. When a carry, which has propagated from a lower order, terminates at a particular bit position, the sum digit of the position where the carry terminates is a 1; 4. When the number of carries which have terminated equals the number of carries which have started, the addition is complete.

The left-hand drawing shows adding circuitry 5, associated with one binary order, and counting and compare circuitry 7, common to all binary orders. The adding circuitry for each other binary order is identical to circuitry 5. Circuitry 5 includes a conventional full-adder 55 (which has two operand inputs A and B, a carry input, a sum output, and a carry output), bistable flip flops 56 and 57, AND's 58, 59, 60 and 61, and inverter 62.

The addition is performed in two time intervals T1 and T2. During period T1, AND's 58 and 59 are conditioned by inputs T1 and flip flops 56 and 57 are respectively set to on, if the associated output from the adder 55 is a 1. Flip flop 56 is set to on, when the operand bits A and B are either both 0 or both 1. That is, flip flop 56 is set to on, when the associated position can terminate a car...