Browse Prior Art Database

Two Input Data Latch

IP.com Disclosure Number: IPCOM000096997D
Original Publication Date: 1962-Mar-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

Homan, ME: AUTHOR [+2]

Abstract

The circuit is a two input data latch and is an improvement on the single input data latch disclosed in U. S. Patent No. 3,005,112, R.M. Meade. NAND logic is employed, as contrasted with current switching logic in the patent. This circuit minimizes the number of logic circuits required to perform data latching without any limitations with respect to the two input signals. The circuit also provides a preselected output signal in the event both input signals are present at the same time.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 53% of the total text.

Page 1 of 2

Two Input Data Latch

The circuit is a two input data latch and is an improvement on the single input data latch disclosed in U. S. Patent No. 3,005,112, R.M. Meade. NAND logic is employed, as contrasted with current switching logic in the patent. This circuit minimizes the number of logic circuits required to perform data latching without any limitations with respect to the two input signals. The circuit also provides a preselected output signal in the event both input signals are present at the same time.

The circuit includes gates 20 and 22. The former is a negative ORINVERT (- O1) circuit. The latter is a positive AND-INVERT (AI) circuit. The -OI 20 input line is normally positive and becomes negative when a turnoff signal is present. The AI 22 input line is normally negative and becomes positive when a turn on signal is present. The outputs from -OI 20 and AI 22 are supplied to the same logic circuits. One logic circuit is a set-on trigger 24 comprising -OI 25 and AI 28 connected to form a latch. The other logic block is set-off gate 26. A timing signal is supplied to the set-on 24 and to the set-off 26. The output from 24 trigger is supplied to control trigger 30 as one input and as another input to the setoff 26. Set-off 26 provides second inputs to control trigger 30 and to gates 20 and 22. Control trigger 30 comprises -OI 32 and AI 34 connected to form a latch. Control trigger 30 is connected to an output circuit 36 and is also returned to gate 20 as a third input.

Wit...