Browse Prior Art Database

Tag-Addressed Memory

IP.com Disclosure Number: IPCOM000097002D
Original Publication Date: 1962-Mar-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 3 page(s) / 80K

Publishing Venue

IBM

Related People

Seeber, RR: AUTHOR [+2]

Abstract

The tag-addressed memory having vacancy recognition employs a three path core. This is capable of assuming either an active condition in which it is switched between two stable states representing 1 and 0, or an inactive condition, or blocked condition. Here, the core is saturated with upward flux in the left hand path and downward flux in the middle and right hand paths.

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Tag-Addressed Memory

The tag-addressed memory having vacancy recognition employs a three path core. This is capable of assuming either an active condition in which it is switched between two stable states representing 1 and 0, or an inactive condition, or blocked condition. Here, the core is saturated with upward flux in the left hand path and downward flux in the middle and right hand paths.

In blocked state, any normal current applied to winding 1 has no effect on the core. The only way that the core can be brought out of blocked condition is to apply current to winding 2 in the direction opposite to the direction of the arrow I(1). A proper amount of current has the net effect of nearly zero flux in the left hand path and a clockwise flux about aperture 3. This is the set state of core. From the set state of a core, if current is applied to the winding 1 in the direction opposite to the direction of arrow I(2), the direction of the flux about aperture 3 changes from the clockwise to the counterclockwise direction leaving the core in the primed state.

To write, each word register is tested by a write control circuit for vacancy to determine if there is room to enter more data.

This is done by applying a positive vacancy test signal on line 4. Assuming that Word 1 is occupied, cores V 11 and V 12 are blocked and core V 13 is set prior to the application of the vacancy test. Since V 12 is blocked, the vacancy test does not effect the core state. It does cause V 13 to become primed. That, in turn, generates a positive output signal on line 5. This passes through amplifier A 14 and is carried to test the following word register. If only the Word 9 register is vacant, cores V 91 and V 92 are set and core V 93is blocked.

The vacancy test causes V 92 to become primed. Since V 93 is blocked there is no output on line 6. Therefore, no all-occupied signal is generated on line 7. When V 92 is primed, a positive output is generated on line 8. Since amplifier A 93 responds only to negative inputs, only amplifier A 92 generates a positive signal of amplitude I(m) on a line 9. This passes through the left hand aperture of Tag and Data cores in Word 9 register to block each of these cores.

At this point, a negative write signal on line 4 re-establishes the initial condition in V 13 and causes V 92 to resume the set state. Therefore, a negative pulse at the input of A 92 causes a negative current of one half I(m) to pass over the line 9. At the same time that the negative write signal is applied to line 4, a positive write signal on the line 10 gates the entry register ET1...ET5, ED1...ED7. These give alternative outputs of opposite polarity in response to stored binary numbers. The coincident positive inputs from the entry register and from line 10 cause write gates W11...W53...W1...W7 to generate a positive current of one half I(m) on a corresponding output line 11 associated with gate W51.

Assuming that the tag of the word to be stored has a...