Browse Prior Art Database

Binary Multiplication

IP.com Disclosure Number: IPCOM000097034D
Original Publication Date: 1962-Apr-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 3 page(s) / 62K

Publishing Venue

IBM

Related People

Blaauw, GA: AUTHOR [+4]

Abstract

Binary multiplication is effected by, developing partial multiplicand (MC) multiples through shifting the MC under control of the multiplier (MP), adding the partial multiples thus developed to form MC multiples, accumulating the multiples by adding them to an accumulator register.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 53% of the total text.

Page 1 of 3

Binary Multiplication

Binary multiplication is effected by, developing partial multiplicand (MC) multiples through shifting the MC under control of the multiplier (MP), adding the partial multiples thus developed to form MC multiples, accumulating the multiples by adding them to an accumulator register.

The MC is initially stored in MC register 1 and the MP in MP register 2, The MP and MC registers each store thirty-two binits, each of which is a bit 1 or not-bit 0. A 4-binit byte of MC is made available to each of two shift units A and B. These shifters respond to respective 2-binit portions of the MP to provide MC multiples. Shift unit A provides MC multiples x0, x1, x2 and x(-1) via 4-binit adder I to temporary storage 6. Developing the x2 multiple causes a shift beyond the capability of adder I in which case the high order bit from A shifter passes to temporary storage 6. B shifter provides multiplicand multiples x0, x4, x8 and x(-4) to 4-binit adder I, with two or three overflow binits passing to temporary storage 6 depending upon the shift selected.

The low-order four binits of temporary storage 6 pass to adder II, where they are combined with the content of accumulator 8. The result is stored back in accumulator 8. On the next step, the next higher four binits of the MC in MC register 1 pass via A shifter and are combined with the high-order four binits of the previous pass from temporary storage 6. These feed around to adder I. Any carry from a previous partial MC multiple in Adder I is inserted and a total result accumulated via adder II to accumulator register 8.

Separate controls exist for the A and B shifters. Shift control A controls the A shift unit; shift control B controls the B shift unit. Four binits of the MP in MP register 2 are examined by circuit elements 11...19 to provide selectivity to A and B shift controls. The low-order two binits of the effective MP byte are impressed upon half-adders 16 and 17 together with any carry held over from the previous MP byte which is retained in carry trigger 11.

Half-adders 16 and 17 provide selection signals to shift control A according to the indicated truth table. Their outputs als...