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Browse Prior Art Database

Synchronizable Clock

IP.com Disclosure Number: IPCOM000097040D
Original Publication Date: 1962-Apr-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 29K

Publishing Venue

IBM

Related People

Day, KB: AUTHOR

Abstract

The clock for a tape reading and recording machine, normally constant in frequency, has its phase incrementally adjustable to maintain it substantially in synchronism with tape signals, not wholly uniform in timing.

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Synchronizable Clock

The clock for a tape reading and recording machine, normally constant in frequency, has its phase incrementally adjustable to maintain it substantially in synchronism with tape signals, not wholly uniform in timing.

Data signals, consisting of groups of pulses representing 1's separated by blank spaces representing 0's are received on line 12. These are temporarily stored individually in bit register 13, a settable trigger circuit. Delay circuit 15 receives the 1 signals. It delays it for a time of about one-half of the nominal pulse interval. Output line 17 of delay 15 is connected to one input terminal of OR 18. Its output line 19 is energized to reset bit register 13 and to transfer the bit into shift register 14.

When a 0 is present on line 12, line 17 is not energized. The shift pulse must be otherwise provided to change denominations in shift register 14. An oscillator 21, having a frequency output which is a multiple of the nominal input pulse frequency, feeds the units order of binary counter 22 and provides a pulse on line
23. The resulting pulses on line 19 are the shift pulses for 0 signals on input line
12.

Trigger 24 is connected by line 25 to counter 22. Trigger 24 is settable to an on state by each 1 pulse on line 12. It is reset off by the same pulse after passing through delay 15. When trigger 24 is on, it applies a voltage through line 25 to the reset terminal of counter 22. This holds counter 22 at start reading, so that, w...