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Instruction Address Buffering

IP.com Disclosure Number: IPCOM000097042D
Original Publication Date: 1962-Apr-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 3 page(s) / 55K

Publishing Venue

IBM

Related People

Stetler, WC: AUTHOR

Abstract

In this arrangement, instructions are processed at high speed and stored in a buffer for later execution. Also, an interrupt system initiates a correction routine at the end of execution of any instruction for which a condition, requiring departure from normal processing, is detected. The address of the instruction following the one which causes the interrupt must be available to enable re-entry into the program after interrupt routines.

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Instruction Address Buffering

In this arrangement, instructions are processed at high speed and stored in a buffer for later execution. Also, an interrupt system initiates a correction routine at the end of execution of any instruction for which a condition, requiring departure from normal processing, is detected. The address of the instruction following the one which causes the interrupt must be available to enable re-entry into the program after interrupt routines.

The circuitry regenerates the re-entry address from the address of the next instruction which was to be fetched for processing. This is effected by subtracting a counter value from the next instruction address. This shows how many instructions were stored in the buffer waiting for execution at the time of the interrupt. An Instruction Counter Register (ICR) 1 controls the fetching of instruction words from memory and through the + 1 Adder 2 and Latch (LTH) 3 has its reading increased by 1 as each instruction is fetched. The fetched instructions are stored in sequence in an instruction execution buffer until used. Counter 4, large enough to count the number of half-words which may be stored in the execution buffers, normally starts at 0... 0.0 and has its output value increased by 1 in Adder 5 and by 1/2 in Adder 6. As a half-word instruction is loaded into the execution buffers, the Adder 6 output is held in Latches 7 to prevent race conditions and then passed through AND's 8 into Counter 4. Similarly, loading of a full-word instruction causes the value in Adder 5 to be passed through Latches 9 and AND 10 into Counter 4.

The value in Counter 4 also passes through AND's 11 and OR's 12 to 1/2 Subtractor 13 and 1 Subtractor 14. The outputs of these are latched in Latches 15 and 16 and passed through AND's 17 and 18 into Counter 4 at the completion of execution of a 1/2 word or a full-word instruction, respectively.

The Counter 4 value indicates the difference between the address (in ICR 1) of the next instruction to be fetched from memory and the address of the next instruction to be executed from the execution buffer store. Therefore, subtraction of the counter value from the value in ICR 1 is the address of the first instruction to be executed after an interrupt operation. The difference between the values of the ICR 1 and Counter 4 is dete...