Browse Prior Art Database

Error injection method for ASICs

IP.com Disclosure Number: IPCOM000097067D
Original Publication Date: 2005-Mar-07
Included in the Prior Art Database: 2005-Mar-07
Document File: 8 page(s) / 152K

Publishing Venue

IBM

Abstract

Disclosed is a method to inject internal errors into an ASIC device which has no internal error inject logic built-in. It is not uncommon for modern ASICs to include some sort of error injection logic in their design. This logic could, for example, invert a bit on a data or address bus to deliberately cause a parity error on that bus. Such a function would be used during the bring-up testing of the ASIC (prior to customer release) in order to determine whether the ASIC design can successfully detect and deal with an internal bit error. However, these functions are not always included within an ASIC for one or more of the following reasons: 1. The amount of logic an ASIC can consist of is ultimately limited by the physical silicon area on which the design must be laid. More logic entails more area which in turn means extra cost to the manufacture of the ASIC. As error injection functions are superfluous to the actual functionality of the ASIC (they are only used during development), these functions may not be embedded into an ASIC in order to keep costs down. 2. Additional logic would also increase the amount of wiring. Wirability and timing constraints may be harder to meet with the addition of internal error inject logic. 3. Design of error inject functions also entails extra development and test effort. Inclusion of such functions within an ASIC design may be omitted in order to save development cost and expense. Disclosed is a method to inject internal parity errors within an ASIC which does not itself possess built-in error inject facilities due to the reasons described above.

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Page 1 of 8

Error injection method for ASICs

Disclosed is a method to inject internal errors into an ASIC device which has no internal error inject logic built-in. It is not uncommon for modern ASICs to include some sort of error injection logic in their design. This logic could, for example, invert a bit on a data or address bus to deliberately cause a parity error on that bus. Such a function would be used during the bring-up testing of the ASIC (prior to customer release) in order to determine whether the ASIC design can successfully detect and deal with an internal bit error.

    However, these functions are not always included within an ASIC for one or more of the following reasons:

The amount of logic an ASIC can consist of is ultimately limited by the physical

silicon area on which the design must be laid. More logic entails more area which in turn means extra cost to the manufacture of the ASIC. As error injection functions are superfluous to the actual functionality of the ASIC (they are only used during development), these functions may not be embedded into an ASIC in order to keep costs down.

Additional logic would also increase the amount of wiring. Wirability and timing

Inclusion of such functions within an ASIC design may be omitted in order to save development cost and expense.

    Disclosed is a method to inject internal parity errors within an ASIC which does not itself possess built-in error inject facilities due to the reasons described above.

    An existing alternative to built-in error inject is to use a protocol exerciser which is able to communicate with the ASIC using the interface protocol the ASIC is designed with. For example, for today's set of PCI protocols many bus exercisers exist on the market. The exerciser can be set up to transfer bad parity to an ASIC under test in order to verify the ASIC's ability to detect the error. However, this method may not be suitable for verifying parity checkers which exist deeper inside the ASIC. As shown in Figure 1, an internal data path within an ASIC may have more than one parity checker along it. One may be placed at the port at which incoming data arrives into the ASIC (shown in green). Others will be positioned further along the data path and deeper inside the ASIC (shown in purple). The green parity checker may not be able to be turned off due to design constraints or the requirements of the interface protocol. Thus when the bus exerciser transfers bad parity to the ASIC, during a test, the first parity checker in line will detect the error and the transfer will halt (due to the error being detected). The parity error will never propagate to the purple parity checkers further along the data path and these will never be tested.


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constraints may be harder to meet with the addition of internal error inject logic. Design of error inject functions also entails extra development and test effort.

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Figure 1: Organisation of parity checkers within an ASIC

The method (whic...