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High Speed, Self-checked, BCD Adder

IP.com Disclosure Number: IPCOM000097100D
Original Publication Date: 1962-May-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 3 page(s) / 54K

Publishing Venue

IBM

Related People

Hsiao, MY: AUTHOR [+2]

Abstract

An unchecked binary coded decimal adder, shown in the upper lefthand drawing, is converted into a fully-checked adder, shown in the lower drawing. The sums S1... S8, of the unchecked BCD adder are generated in accordance with the following equations: S1 = U1; S2 = U2V Ca; S4= U4 V Ca V C2'; S8= U8V C4'. V represents the Exclusive Or function.

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High Speed, Self-checked, BCD Adder

An unchecked binary coded decimal adder, shown in the upper lefthand drawing, is converted into a fully-checked adder, shown in the lower drawing. The sums S1... S8, of the unchecked BCD adder are generated in accordance with the following equations: S1 = U1; S2 = U2V Ca; S4= U4 V Ca V C2'; S8= U8V C4'. V represents the Exclusive Or function.

Since the parity of the left-hand side of each equation is equal to the parity of the right-hand side, the parity of the left-hand side of all four equations is equal to the parity of the right-hand side of all four as follows: 1. S1 VS2VS4VS8 = (U1) V (U2VCa) V (U4VCaVC2') V(U8VC4') Ca appears twice in this equation, and therefore cancels out, so that equation 1 becomes: . 2. S1 VS2VS4VS8 = U1 V U2V U4V U8VC2' VC4'

The parity of all the input bits X1 - X8 (Px), of all of the input bits Y1 - Y8 (Py) and of all the carry inputs C and C1 - C4 (Pc) are related as follows to the parity of all the sum outputs U1 = U8 (Pu): 3. Px V Py V Pc = Pu; and 4. Pu=U1VU2VU4VU8

Substituting equations 3 and 4 into equation 2: 5. S1 V S2VS4VS8 = PxV PyVPcVC2'VC4'

Due to the inherent nature of the Exclusive Or function, equation 5 may be rewritten: 6. (S1 YS2V S4V S8) V (C2' VC4') = (PxV Py) V Pc, and 7. Pc = C V C1 V C2VCC4, so that 8. (S1 VS2VS4VS8) V (C2' VC4') = (PxV Py) V(C VC' V C2VC4)

Equation 8 shows the relationship used in the lower drawing to check the BCD adder stage. If thereis an error, the right side of equation 8 is not equal to the left side and an error signal is generate...