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Browse Prior Art Database

Logical Circuits And Memory

IP.com Disclosure Number: IPCOM000097102D
Original Publication Date: 1962-May-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 3 page(s) / 83K

Publishing Venue

IBM

Related People

Scriver, AJ: AUTHOR [+2]

Abstract

The arrangement provides entrance into and retrieval from a sequence of registers, constituting an associative memory, in the order in which data is received, e. g., from a computer. The logical circuits operate to put any word received into the first vacant register, and to read out the first register having the proper tag. Repetitive readout is performed to retrieve a plurality of words with the same tags, making it possible to store and retrieve groups of data in a known sequence.

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Logical Circuits And Memory

The arrangement provides entrance into and retrieval from a sequence of registers, constituting an associative memory, in the order in which data is received, e. g., from a computer. The logical circuits operate to put any word received into the first vacant register, and to read out the first register having the proper tag. Repetitive readout is performed to retrieve a plurality of words with the same tags, making it possible to store and retrieve groups of data in a known sequence.

In the diagram, the four columns at the right comprise register positions in which the actual information bits, both tag and data, are stored. The four blocks in the top row comprise entry register positions common to all of the word registers in the corresponding column. The four blocks in the bottom row similarly comprise exit register positions common to all of the word registers in the same column. Each horizontal row except the top and bottom rows comprise a word register in which one unit of information, or word, is stored.

The three vertical columns of blocks at the left comprise control circuits. The three blocks in the top row are common to the entire memory. Each pair of blocks in the subsequent rows provide vacancy control for the word register represented by that row of blocks. The memory is shown as comprising four word registers each including two data bits, Data 1 and Data d, and two tag bits, Tag 1 and Tag
t. Each register is controlled by corresponding vacancy circuits, there being a Vacancy register and a Vacancy Echo register used to indicate the original status of the word register for each word register.

A timing circuit provides off currents when information passes between the memory and the associated data processing apparatus. It provides on currents when data is to be transferred within the memory. The output lines of the timing circuit are arranged in three pairs, each pair having an on line 102 and an off line 103. At all times, either on lines 102 or the off lines 103 are operative. An Entry- Exit register responds to computer instructions to transfer data to or from the word registers during an on period. There are three pairs of output lines from the Entry-Exit register, one pair 105, 106 being a continuation of the On-Off pair 102, 103 from the timing circuit. The other two pairs each have one line 107, operative during an entry operation, and one line 108, operative during an exit operation. Just as in the case of the timing circuit output lines, one or the other of each pair 107, 108, but never both, are operative at all times. The off line 106 and on line 105 control the transfer of vacancy bits between the Vacancy Entry, Vacancy and Echo registers throughout the memory. The Off or Exit and Entry lines 112, 109 together control the selection of word registers on the basis of the vacancy bit. Before beginning to thread through the Word 1 register, the Entry line 109 is split into two lines,...