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Multiapertured Core Logic Circuit

IP.com Disclosure Number: IPCOM000097118D
Original Publication Date: 1962-May-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Betts, R: AUTHOR

Abstract

Binary information stored in one core is transferred to a subsequent core during discharge of the coupling capacitor between them.

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Multiapertured Core Logic Circuit

Binary information stored in one core is transferred to a subsequent core during discharge of the coupling capacitor between them.

A core is in 0 state, if the whole flux is in a counterclockwise direction about the central aperture. It is in the 1 state, if the flux is down in leg III and up in leg
IV. A transfer loop embraces output leg III of a core and input leg I of the subsequent core. This is in a series circuit including a capacitor C. A second input leg I' in each core provides a side entry.

Assuming that only core K(n-1) is in the 1 state, if the W drive line is energized, K(n-1) is reset to 0. This provides a counterclockwise current in loop n-1, which charges C(n-1) but does not affect Kn. When the output voltage of K(n-1) becomes smaller than the voltage on C(n-1), the current in loop n-1 reverses and switches leg I of K(n) upward. Also leg III of K(n) switches downward providing a clockwise current in loop n, which charges C(n). This capacitor loads core K(n) during the initial switching but aids in completing the switching of leg III when it discharges. K(n+1) is held in the 0 state by the W pulse. The shorted winding encircling leg IV prevents any flux change in it.

A pulse on line X switches leg I of K(n) downward, so that, when K(n) in turn is reset by Y and Z pulses for transfer to K(n+1), no voltage is generated in loop n-1.

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