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Two Dimensional Memory Accessing

IP.com Disclosure Number: IPCOM000097120D
Original Publication Date: 1962-May-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 91K

Publishing Venue

IBM

Related People

Busch, DF: AUTHOR

Abstract

The circuit is for accessing a magnetic core memory array. Access is parallel by bit and serial by character or digit. No inhibit winding is employed.

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Two Dimensional Memory Accessing

The circuit is for accessing a magnetic core memory array. Access is parallel by bit and serial by character or digit. No inhibit winding is employed.

In writing, assume, for example, a 2 out of 5 bit code is employed and that writing is effected into bits 1 and 3 in character 1 of word 1. The word 1 line is driven in the write direction by selective drive 10 (a bidirectional driver), character 1 gate is closed and the 1 and 3 bit drivers are activated to drive the corresponding bit lines. This causes cores 11 and 13 to be set.

To read out character 1 of word 1, word 1 line is driven in the read direction by drive 10, read driver 14 is activated and character 1 gate is closed. In this case, cores 11 and 13 representing the 1 and 3 bits in character 1 are reset and a voltage is induced in the 1 and 3 bit sense lines. For simplification, only the 1 bit sense line and the associated sense amplifier are shown. However, each bit of a character has a respective sense line and an associated amplifier.

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