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Browse Prior Art Database

High-Speed Core Memory

IP.com Disclosure Number: IPCOM000097168D
Original Publication Date: 1962-Jun-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 3 page(s) / 70K

Publishing Venue

IBM

Related People

Foglia, HR: AUTHOR

Abstract

A magnetic core memory which accepts information at a fast rate by walking a core, during writing, along its minor hysteresis loop, is accompanied by a predetermined delay for access of this information. See the article directly preceding this one. Such article describes a magnetic memory having high-speed access which is not accompanied by core heating and the power limitations of a diode selection matrix. It accepts information Mt a high rate but the information accepted is not immediately available for readout.

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High-Speed Core Memory

A magnetic core memory which accepts information at a fast rate by walking a core, during writing, along its minor hysteresis loop, is accompanied by a predetermined delay for access of this information. See the article directly preceding this one. Such article describes a magnetic memory having high- speed access which is not accompanied by core heating and the power limitations of a diode selection matrix. It accepts information Mt a high rate but the information accepted is not immediately available for readout.

A coincidence of inputs on a word drive line and a bit drive line overcomes the saturation remanence switching threshold of a selected core and the core is partially switched. The bit drive line is further energized by at least two further impulses to walk the core partially switched along its mi or hysteresis loop to a further partially switched remanent state. Necessarily, in such a system, since it takes at least three cycles to set the core sufficiently to obtain a good output signal, availability of information for readout is delayed.

The delayed information retrieval problem is avoided by employing auxiliary registers in the circuitry of this article. Core matrix memory 10 has word write selection and drive 12, word reset selection and drive 14 a bit drive 16 and an output sense 18 coupled to it. The drive 16 is energized by input register 20 while the sense 18 is connected to output register 22. Both drives 12 and 16 are gated by an output from OR 24. The reset 14 is gated by means of AND 26. Information from output register 22 is connected to a memory output line through AND 28. Auxiliary word registers 30, 32 and 34 are provided each having information entered in them and controlled by corresponding AND's 36, 38 and 40, respectively.

Auxiliary controls are provided in which the addresses for the information entered into auxiliary word registers 30, 32 and 34 are stored in registers 42, 46 and 48, respectively, having corresponding compare circuitry 50, 52 and 54. Since information capable of being read-out and recognized is to be stored in memory 10 by the use of an original and at least two other auxiliary cycles, the memory operates on a three phase clock system A, B and C....