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Digital to Analog Converter

IP.com Disclosure Number: IPCOM000097169D
Original Publication Date: 1962-Jun-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Related People

Linardos, SG: AUTHOR

Abstract

The digital to analog converter employs saturable reactors as its active elements. In set condition, bit latch 10 provides a current which saturates reactor 12, 14 or 16 alone or in combination. Each reactor exhibits a very low impedance in parallel with driveline 18. Driveline 18 is connected to A. C. power source 19. In reset condition, Latch 10 does not provide current to a reactor which, therefore, exhibits a very high impedance in parallel with driveline 18. Therefore, only the resistors R1, R2 and/or R3 in series with the respective reactor receiving a set signal will appear as load across the driveline 18. Since these resistors are binary weighted, i. e., R1 = 2R2 = 4R3, the current I in the driveline 18 has an analog magnitude equal to the binary number in latch 10.

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Digital to Analog Converter

The digital to analog converter employs saturable reactors as its active elements. In set condition, bit latch 10 provides a current which saturates reactor 12, 14 or 16 alone or in combination. Each reactor exhibits a very low impedance in parallel with driveline 18. Driveline 18 is connected to A. C. power source 19. In reset condition, Latch 10 does not provide current to a reactor which, therefore, exhibits a very high impedance in parallel with driveline 18. Therefore, only the resistors R1, R2 and/or R3 in series with the respective reactor receiving a set signal will appear as load across the driveline 18. Since these resistors are binary weighted, i. e., R1 = 2R2 = 4R3, the current I in the driveline 18 has an analog magnitude equal to the binary number in latch 10.

The analog current I is coupled through transformer 20 to output winding 22. The phase of the analog output in winding 22 is controlled by sign latch 24 driving saturable reactor 26 or 28. The respective reactor switches one of the transformer 20 input windings 30 or 32 into the driveline 18. The selected winding defines the phase of the output signal at winding 22.

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