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Correcting Burst Errors

IP.com Disclosure Number: IPCOM000097179D
Original Publication Date: 1962-Jun-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

D'Antonio, RA: AUTHOR [+2]

Abstract

This circuit detects and corrects bursts of errors in a train of binary data bits. In the IBM Journal of Research and Development, July, 1960, in the article commencing on page 329, a circuit is shown for generating error vectors. These vectors are stored in a shift register and are used to correct bursts of errors coming in on the input transmission line. The use of table look-up become; inefficient as the number of errors to be corrected in a single burst increases. Where the number of errors to be corrected is large, the deciding circuit in the above drawing is considerably more efficient.

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Correcting Burst Errors

This circuit detects and corrects bursts of errors in a train of binary data bits. In the IBM Journal of Research and Development, July, 1960, in the article commencing on page 329, a circuit is shown for generating error vectors. These vectors are stored in a shift register and are used to correct bursts of errors coming in on the input transmission line. The use of table look-up become; inefficient as the number of errors to be corrected in a single burst increases. Where the number of errors to be corrected is large, the deciding circuit in the above drawing is considerably more efficient.

The error vectors (Z vectors) which are stored in register B in Figure 2 of the article are instead read into the U register and the L register. These registers form one continuous register in which all the error vectors are stored. The L register is then sensed for all 0's by AND 10. If this test fails, the L and U registers are shifted right one position. The data from certain pre-assigned positions is added mod-2 and the sum fed back into the LR position. Simultaneously, a bit of data is passed to the sink. This test for all 0's is repeated until an all-0 condition is detected in L.

If after N (N = B + R) shifts the all-0 condition is still not detected, such indicates that an uncorrectable error has occurred. When an all-0 condition is detected by AND 10, the priority scan logic circuit 12 is energized to start a scan of U starting with the B posi...