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Missing Clock Pulse Detector

IP.com Disclosure Number: IPCOM000097186D
Original Publication Date: 1962-Jun-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 37K

Publishing Venue

IBM

Related People

Heffernan, RH: AUTHOR [+4]

Abstract

The detector circuit indicates a missing pulse in a clock pulse train. Four clock pulse trains I, II, III and IV are applied to input terminals 10, 12, 14 and 16, respectively, of the OR. As long as all pulses are present on OR inputs, diode D2 of AND 1 is reversely biased by capacitor C1. Also, diode D3 is reversely biased by the cutoff condition of transistor Q2. Under the condition that one input clock pulse is not present at an OR, C1 discharges sufficiently to permit D2 to conduct. This turns off transistor Q1 and the voltage level at output terminal 18 rises. As a result, Q2 turns on causing D3 of AND 1 to conduct and latch the detector circuit. The output on terminal 18 remains up until a positive potential reset signal is applied to reset terminal 20 of AND 2.

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Missing Clock Pulse Detector

The detector circuit indicates a missing pulse in a clock pulse train. Four clock pulse trains I, II, III and IV are applied to input terminals 10, 12, 14 and 16, respectively, of the OR. As long as all pulses are present on OR inputs, diode D2 of AND 1 is reversely biased by capacitor C1. Also, diode D3 is reversely biased by the cutoff condition of transistor Q2. Under the condition that one input clock pulse is not present at an OR, C1 discharges sufficiently to permit D2 to conduct. This turns off transistor Q1 and the voltage level at output terminal 18 rises. As a result, Q2 turns on causing D3 of AND 1 to conduct and latch the detector circuit. The output on terminal 18 remains up until a positive potential reset signal is applied to reset terminal 20 of AND 2.

The number of clock pulse trains to the OR and the time interval S between sequential pulses determines the values for R1 and C1. The voltage level at output terminal 22 falls when the voltage level at terminal 18 rises. Therefore, the voltage levels at output terminals 18 and 22 are used as 1 and 0 respectively, to indicate the missing clock pulse.

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