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Hybrid Tunnel Diode-Transistor Circuit

IP.com Disclosure Number: IPCOM000097192D
Original Publication Date: 1962-Jun-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 31K

Publishing Venue

IBM

Related People

Widmer, AX: AUTHOR

Abstract

The circuit performs reliable D. C. voltage translation from galliumarsenide or silicon tunnel diode levels to germanium transistor levels.

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Hybrid Tunnel Diode-Transistor Circuit

The circuit performs reliable D. C. voltage translation from galliumarsenide or silicon tunnel diode levels to germanium transistor levels.

Germanium diode 1 couples tunnel diode latch 2 and grounded-emitter transistor arrangement 3. The resulting voltage-current characteristic at point P is such that latch 2 controls arrangement 3 between complete cutoff and full saturation.

While tunnel diode 4 is in a low voltage state, coupling diode 1 is slightly forwardly biased by voltage sources 5 and 6 connected along resistors 7 and 8, respectively. The emitter-base junction 9 is slightly reversely biased so that arrangement 3 is fully cutoff. When tunnel diode 4 is switched to a high voltage state, coupling diode 1 is driven into higher conduction. The emitter-base junction 9 is forwardly biased to a point where arrangement 3 is driven to saturation.

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