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Serial-parallel Shift Register

IP.com Disclosure Number: IPCOM000097225D
Original Publication Date: 1962-Jul-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 30K

Publishing Venue

IBM

Related People

Gindi, AM: AUTHOR

Abstract

A shift register is achieved by providing one storage stage for each group of three shift register stages as shown. This is instead of one storage stage for each shift register stage or one for each complete shift register as effected previously.

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Serial-parallel Shift Register

A shift register is achieved by providing one storage stage for each group of three shift register stages as shown. This is instead of one storage stage for each shift register stage or one for each complete shift register as effected previously.

Each stage 1...22 is settable to either one of two stable conditions to represent 1's and 0's. Each stage is provided with a data input such as the inputs 101... 122. Each stage is also provided with a timing input such as inputs 201...222. The timing inputs gate signals on the data inputs so as to set each stage according to the signal on its data input at the appropriate time.

Each stage in column two 2, 6...22 is a storage position. Columns one, three and four are shift positions. In operation, timing signals T1... T4 are sequentially applied to respective timing lines 231...234. In a first cycle of operation, signal T1 is applied to line 231, then T2 to 232, followed by T3 on 233 and then T4 on 234. Thus, data is shifted from all the registers 1, 5...21 in column one to corresponding registers 2, 6...22 in column two. Then, data is shifted from the input on line 101 into position 1, from position 4 to 5, from position 8 to 9, from position 12 to 13, from position 16 to 17, from position 20 to 21, all in response to T2 on line 232. Next, data stored in column three is shifted into column four by T3 on line 233. Finally, data is shifted out of storage column two into column three by T4 on...