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Priority Line Selecting Circuitry

IP.com Disclosure Number: IPCOM000097260D
Original Publication Date: 1962-Aug-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Related People

Muir, J: AUTHOR

Abstract

The completing of but one transmission line Ai-Ao, Bi-Bo, Ci-Co, or Di-Do at a time essentially in the order of appearance of signals at the input side Ai, Bi, Ci or Di is afforded with conventional And, Or and Inverter logic blocks.

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Priority Line Selecting Circuitry

The completing of but one transmission line Ai-Ao, Bi-Bo, Ci-Co, or Di-Do at a time essentially in the order of appearance of signals at the input side Ai, Bi, Ci or Di is afforded with conventional And, Or and Inverter logic blocks.

The arrangement can be expanded to almost any number of lines. A toggle circuit 10 has two And's 12 and 14 and two Or's 16 and
18. The arrangement shown is for complemented transistor resistor logic, but other logic an be applied readily. With all input lines Ai, Bi, Ci, Di down, all output lines likewise are down. The intracircuit lines are up or down as indicated by the letters U or D.

The outputs of Or's 16 and 18 are dissimilar. The Or 16 or 18 that turns up U in the initial operating condition depends on the relative response time of the two individual circuits. This is determined by exact values of the components of the Or's.

An incoming signal level rising as at line input Ci, effects a corresponding output line level rise, at the line output. The output levels Co of the logic blocks 22, 34, 14, 16, 18, 26 and 28 are then reversed as the circuit 10 toggles to the opposite condition.

Should another incoming signal level rise, as at line input Bi, while the level at the prior raised input Ci is still up, the output levels of the logic blocks 32 and 33 are reversed but circuit 10 is not toggled.

With the other incoming line input Bi waiting, the dropping of input level at the prior raised input C...