Browse Prior Art Database

Superconductive Transmission Line Memory

IP.com Disclosure Number: IPCOM000097298D
Original Publication Date: 1962-Sep-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

Freiser, MJ: AUTHOR [+2]

Abstract

The superconductive memory is in the form of a transmission line 10, consisting of superconductive strip 12 laid down above and insulated from superconductive shield 14 by a layer of dielectric material.

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Superconductive Transmission Line Memory

The superconductive memory is in the form of a transmission line 10, consisting of superconductive strip 12 laid down above and insulated from superconductive shield 14 by a layer of dielectric material.

Strip 12 has a number of gate sections 12 A...12 F, each of which is associated with a control conductor 20 A...20 F. A bias current Ib is continuously applied to line 10. The control conductors are energized to introduce resistance into the gate conductor. This resistance is maintained by the bias current due to heat latching after the control conductors are deenergized.

Each of the gate sections is interrogated in response to the application of a single interrogation signal Is. This, as it proceeds down the line from left to right, produces a reflection Ir at each gate which is in a resistive state. These reflections are sensed at the left hand end of the line. The characteristic impedance of the line and the resistance of the individual gate sections are such that only a small portion of the energy in the interrogation signal is reflected at each resistive gate and that the reflections are of essentially the same magnitude.

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