Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

High Speed Character Recognition

IP.com Disclosure Number: IPCOM000097307D
Original Publication Date: 1962-Sep-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 36K

Publishing Venue

IBM

Related People

Lumpkin, C: AUTHOR [+2]

Abstract

The circuit converts the video signal output of character scanning apparatus 9 into useful data. This, when fed into character recognition apparatus 8, produces a coded representation of the recognized character. Recognition apparatus 8 has a line length counter and an intersection counter per line of character resolution. The circuit discriminates between scanned lines and scanned intersections. It produces output pulses representative of (a) sensed intersections and (b) the beginning and end portions of sensed lines.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 55% of the total text.

Page 1 of 2

High Speed Character Recognition

The circuit converts the video signal output of character scanning apparatus 9 into useful data. This, when fed into character recognition apparatus 8, produces a coded representation of the recognized character. Recognition apparatus 8 has a line length counter and an intersection counter per line of character resolution. The circuit discriminates between scanned lines and scanned intersections. It produces output pulses representative of (a) sensed intersections and (b) the beginning and end portions of sensed lines.

For example, assume that a line is sensed. The video signal output of scanning apparatus 9, which is representative of the line length, is fed to pulse amplifier 1 and width trigger 2. Both amplifier 1 and trigger 2 are conditioned by minimum detection amplifier 3 to prevent noise from passing through them.

At amplifier 1, a pulse is generated in response to the video signal which is then delayed and passed to gate 4 which may or may not be conditioned.

At trigger 2, which passes only signals exceeding a minimum width, the signal representing the sensed line is passed through and fed to pulse generator
5. Generator 5, responsive to signal level increases, produces an output indicative of the beginning of the sensed line. This output serves (a) to set flip flop 6 whose output deconditions gate 4 and blocks the delayed pulse produced by amplifier 1 and (b) as an input to recognition apparatus 8 where a line length cou...