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Basic Arithmetic System Using Two Terminal Devices

IP.com Disclosure Number: IPCOM000097315D
Original Publication Date: 1962-Sep-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 3 page(s) / 85K

Publishing Venue

IBM

Related People

Smith, MG: AUTHOR [+2]

Abstract

A block representation of a four phase, synchronous arithmetic system employing tunnel diodes, parametrons, etc., is shown in A. Elements designated phi 1, phi 2, phi 3, the 4 are operative concurrently during successive phases of the power supply cycle. Leads designated P are connected to control circuitry, not shown, to enable the And's to effect the addition process.

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Basic Arithmetic System Using Two Terminal Devices

A block representation of a four phase, synchronous arithmetic system employing tunnel diodes, parametrons, etc., is shown in A. Elements designated phi 1, phi 2, phi 3, the 4 are operative concurrently during successive phases of the power supply cycle. Leads designated P are connected to control circuitry, not shown, to enable the And's to effect the addition process.

Addend and augend are stored in Registers X and Y, respectively, each comprising dynamic Bit Circulators C1...C64. Each bit circulator, shown in B, includes a number of stages equal to the number of phases in the power supply cycle. During the quiescent state, information is recirculated and thus stored along these stages during the successive phases of the power supply cycle. In each Bit Circulator C(X), the input of Parallel Shift Right-And gate (not required in Bit Circulators C61... C64) is connected to the the 1 Majority circuit of Bit Circulator C(X+4). Add In And gates are required only in Bit Circulators C61... C64 of register Y in which the total sum is to be stored. Addend and augend information is stored in parallel in Registers X and Y via the Read In And gates.

The number of adders, shown as A1... A4, is calculated by N = PQ/C where P is the number of phases in the power supply cycle, C is the number of phases of the power supply cycle required to generate carry information in an adder, and Q is a whole number selected so as to make N equal to a minimum positive integer. Each adder, as shown in C, requires three phases of the power supply cycle to generate sum information and a single phase of the power supply cycle to generate carry information. The first operative phase of Adders A1... A4 occurs during successive phases of the power supply cycle to allow ripple through carry propagation. Carry information from the highest order Adder A4 is fed back to the lowest order Adder A1.

Arithmetic is performed on a byte basis by the...