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Synchronized Time Delay Relay

IP.com Disclosure Number: IPCOM000097317D
Original Publication Date: 1962-Sep-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 29K

Publishing Venue

IBM

Related People

Carman, CD: AUTHOR

Abstract

The synchronized time delay circuit utilizes a PNPN type controlled rectifier 1. On the application of potentials +V and -V to collector 2 and base 3, respectively, capacitor 4 charges exponentially through resistor 5. The potential of emitter 6 approaches that of base 3.

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Synchronized Time Delay Relay

The synchronized time delay circuit utilizes a PNPN type controlled rectifier
1. On the application of potentials +V and -V to collector 2 and base 3, respectively, capacitor 4 charges exponentially through resistor 5. The potential of emitter 6 approaches that of base 3.

Switch 7 is closable by rotating cam 8 to momentarily connect base 3 to ground through resistor 9 and apply a positive going pulse to the base. As the emitter potential asymptotically approaches the base potential, one of these positive going pulses causes the base emitter bias to be reduced to the point where the rectifier fires and, thus, accurately establish a time interval. Switch 10 is closable to reset the timer by discharging capacitor 4.

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