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Parity Check Circuit

IP.com Disclosure Number: IPCOM000097355D
Original Publication Date: 1962-Oct-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 27K

Publishing Venue

IBM

Related People

Gerrand, F: AUTHOR [+2]

Abstract

The parity of a word in a register is determined by modulo-2 adding the contents from one group of triggers of the register into another group. Then, the parity of the modulo-2 sum formed in this other group is determined.

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Parity Check Circuit

The parity of a word in a register is determined by modulo-2 adding the contents from one group of triggers of the register into another group. Then, the parity of the modulo-2 sum formed in this other group is determined.

The 1 output of each flip-flop FF1...FF4 in the lower part of the register conditions two gates of an associated flip-flop FF5... FF8 in the upper part of the register. A pulse P passes through the conditioned gates and switches the associated upper flip-flops. For example, if FF2 is set to 1, it causes switching of FF6. The final condition of FF6 is the modulo-2-sum of the contents of FF2 and FF6.

Logical circuits Add Circ. with half-add properties are each conditioned by the outputs of two upper stages. These Add Circ's sequentially control each other, so that a final one supplies a parity signal for the word in the register. Add Circ. 1 receives a pulse Q and supplies an even or an odd pulse in accordance with the states of the two conditioning upper flip-flops. Add Circ. 2 receives the even or odd pulse from Add Circ. 1 and supplies an even or an odd pulse in accordance with the states of its associated flip-flops. Add Circ. 2 supplies an odd or an even pulse to a parity stage or a parity check circuit.

If it is desired to reset the register to its initial condition, a second pulse P is supplied to the gates of the upper triggers.

If the upper flip-flops are provided with two pairs of gates, each pair being conditioned...