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Logic Circuit

IP.com Disclosure Number: IPCOM000097361D
Original Publication Date: 1962-Oct-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 23K

Publishing Venue

IBM

Related People

Slobodzinski, EJ: AUTHOR

Abstract

(Image Omitted) This Nor consisting of an Or 20 connects to the input of a synchronized inverted 32. The output pulses occur one clock cycle after the input pulses.

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Logic Circuit

(Image Omitted)

This Nor consisting of an Or 20 connects to the input of a synchronized inverted
32. The output pulses occur one clock cycle after the input pulses.

The inverter contains, as asymmetrically conductive devices, a first Esaki diode 22 and, in series with it, a second Esaki diode 40.

Both normally are in their conductive conditions. Input 26 is connected to one end of this series circuit, i. e., to diode 22.

The output of the inverter is available on the line 41 of diode 40 which is connected through a resistance and a line 24 to diode 22. Line 24 receives clock pulses through the clock source 44. Input 26 is further connected through a series connection comprising a differentiating circuit and a normally conductive diode 42 to the output. The differentiating circuit comprises condenser 34 and resistor 36.

On the occurrence of a clock pulse and no input pulse, diode 22 is switched into its high voltage stable condition. By the transmission of the differentiated pulse, diode 40 is also switched into its high voltage condition, so that an output pulse is produced.

When a clock pulse occurs simultaneously with an input pulse, an output pulse is also produced, but due to the influence of the diodes 21 of Or 20 on the load line of diode 22, diode 22 is not switched into its fully conductive condition in the subsequent half-period of the clock pulse sequence. Thus, condenser 34 is discharged only to a minor degree. Consequently, when a clock...