Browse Prior Art Database

Serial Peripheral Adapter

IP.com Disclosure Number: IPCOM000097369D
Original Publication Date: 1962-Oct-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Schaffer, WS: AUTHOR

Abstract

This apparatus is for data interchange by a computer to input-output equipment or another computer.

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Serial Peripheral Adapter

This apparatus is for data interchange by a computer to input-output equipment or another computer.

In A, computer storage 10 transmits data to and receives data from input- output unit (I-O) 11. Unit 28, shown in detail in B, controls this transfer of data. Data from and to storage 10 is read out and read in by successive storage locations under control of clock 20 (B). This generates a timing cycle and operates an address register, not shown, to select these successive locations.

When a timing cycle is generated, a character of data from storage 10 is read into register 29 and then over line 30 to I-O 11. Data from I-O 11, during a readin operation, is read into register 32, through an inhibit mix 33, to storage 10.

Data characters from storage 10 indicative of a particular input output unit to be selected are recognized by a logic unit, not shown, to initiate operation of the selected I-O, e.g., 11, by a signal on line 12. Upon operation of 11, a signal is generated by unit 11 on line 13 to set trigger 14(B). An output 15 from trigger 14 is connected to And's (&'s) 16 and 17. The latter are conditioned by the outputs of &'s 18 and 19, respectively, to generate an output.

Such starts clock 20 to initiate a timing cycle by which a location in storage 10 is selected for the readin or readout of information.

Clock 20, upon operation, transmits a signal on line 21 to turn off trigger 14. This terminates further conditioning of 20 until ano...