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Three Transistor Trigger

IP.com Disclosure Number: IPCOM000097408D
Original Publication Date: 1962-Nov-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Related People

Morris, EF: AUTHOR

Abstract

This trigger circuit employs three transistors of the same conductivity type, either NPN or PNP. Transistor T1 operates as an And to switch transistor T2 in response to proper data and clock inputs. The state of T2 controls the output level. Transistor T3 operates in response to the clock input and to feed back from the output via line F to latch the information. T2, which is normally on, is only turned off by a coincidence of a negative data signal and a positive clock signal. Once off, it is held in that state by the latching action of the feedback circuit F for as long as the clock is negative.

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Three Transistor Trigger

This trigger circuit employs three transistors of the same conductivity type, either NPN or PNP. Transistor T1 operates as an And to switch transistor T2 in response to proper data and clock inputs. The state of T2 controls the output level. Transistor T3 operates in response to the clock input and to feed back from the output via line F to latch the information. T2, which is normally on, is only turned off by a coincidence of a negative data signal and a positive clock signal. Once off, it is held in that state by the latching action of the feedback circuit F for as long as the clock is negative.

The pulse drawing illustrates an example of operation of the circuit. Assume that the data and clock inputs are initially positive and negative, respectively, as shown at T1 and that both T1 and T3 are off. Under these conditions, T2 is held on by the +6 volt base supply and the output is negative. Feedback via line F holds T3 off. When the clock goes positive at T2, no change occurs since the positive data input holds T1 off. However, when the data input goes negative at T3, T1 is turned on pulling the base of T2 down and turning it off. When T2 goes off, the output goes positive.

Positive feedback to the base of T3 allows it to turn on when the clock goes negative at T4. At this time, T3 latches T2 off so that even though the data line goes positive at T5, the positive level is maintained at the output.

When the clock goes positive at T6, T3 i...