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One Shot Capacitor Discharge

IP.com Disclosure Number: IPCOM000097410D
Original Publication Date: 1962-Nov-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 37K

Publishing Venue

IBM

Related People

Clapper, GL: AUTHOR

Abstract

The circuit produces single-shot energization of a load. It is arranged so that only one pulse of energy is supplied to the load per operating cycle.

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One Shot Capacitor Discharge

The circuit produces single-shot energization of a load. It is arranged so that only one pulse of energy is supplied to the load per operating cycle.

The load comprises a plurality of parallel-connected magnetic cores, each having a series resistance and inductance, such as R1L1...RnLn. The load is connected across the terminals of capacitor Q by operation of a Set switch. The charging circuit for Q includes diode D1 and resistor R4, connected between one terminal of Q and the -12V source. The circuit also includes a pair of complementary transistors T1 and T2, connected in a circuit including resistances R5, R6 and R7. A resetting circuit including a Reset key and diode D2 is connected between the emitter of T2 and ground. The transistor pair acts as a latch. This applies a suitable back-biasing voltage on charging diode D1. Thus, the capacitor is decoupled from the charging source.

Normally, the latch is off. That is, both transistors are not conducting. In this state, a charging path is provided for capacitor Q to -12V via diode D1 and resistor R4. When the Set key is depressed, the voltage at point A drops sharply to provide current to the load. As current builds up in the load, capacitor Q charges and the voltage at point B rises. As the voltage at B rises, the voltage at point C also rises as current flows through diode D1. When the voltage at C reaches -6V, the bias on T1 is removed and the voltage at point D drops to -6V.

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