Browse Prior Art Database

Counters

IP.com Disclosure Number: IPCOM000097411D
Original Publication Date: 1962-Nov-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Heilweil, MF: AUTHOR

Abstract

These counters use individual binary trigger stages capable of accepting and providing complementary and nonoverlapping input and output signals.

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Counters

These counters use individual binary trigger stages capable of accepting and providing complementary and nonoverlapping input and output signals.

The upper circuitry shows two stages of a serial binary counter. The counter output of each stage changes to its new value at the rise of each input pulse. Assuming that the last latch, cross-coupled Or-Inverters (OI's) 7 and 8, is in one of its two stable states, And's 1 and 2 receive complementary conditioning signals from the feedback connection. One of these conditioning levels is up. During a first cycle, when input 1 is up and input 2 is down, one of And's 1 and 2 is fired to switch its associated latch, cross-coupled OI's 3 and 4. Neither one of And's 5 and 6 is fired because input 2 is down. During a second cycle, when input 1 goes down, input 2 goes up and one of And's 5 or 6 is fired which switches the latch, cross-coupled OI's 7 and 8 to its other stable state. Thus, energization of one bistable stage with respective true and complement pulses results in sequential and ordered switching of the latches. This constitutes the basic element of a counter. The outputs of stage 1 are complementary and nonoverlapping and provide the required true and complement pulses for the input to the next identical counter stage where a similar sequence of events takes place.

The lower circuitry shows one decimal stage (decade) for a binary coded decimal counter. The counter counts from zero through nine in BCD, and res...