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Error Detection for Computer Instruction Performance

IP.com Disclosure Number: IPCOM000097457D
Original Publication Date: 1962-Dec-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 51K

Publishing Venue

IBM

Related People

Wolff, CH: AUTHOR

Abstract

In response to a digital computer instruction calling for a particular operation to be performed, this logic determines which of a series of timing pulses caused energization of an erroneous number of control lines to the operative elements of the computer.

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Error Detection for Computer Instruction Performance

In response to a digital computer instruction calling for a particular operation to be performed, this logic determines which of a series of timing pulses caused energization of an erroneous number of control lines to the operative elements of the computer.

The Operation Code in the Instruction Register is decoded to energize a single Command Line. The Operation Decoder provides one Command Line input to a plurality of Gates. Each of a series of timing pulses is applied to particular ones of the Gates to energize a particular combination of Control Lines.

The rest of the logic is used to determine and store the odd-even parity of the number of Control Lines energized for each timing pulse. Timing pulse t1 energizes certain Control Lines to cause certain computer functions to be performed. Each Control Line has an associated binary trigger in an Instruction Control Parity Register. When a particular Control Line is energized, the stable state of the associated trigger is changed. The binary output of the Exclusive Or tree in the Parity Generator indicates that an odd (binary 1) or even (binary 0) number of binary 1's are contained in the Parity Register.

Timing pulse t2 causes other Control Lines to be energized and the associated binary triggers in the Parity Register are changed accordingly. Pulse t2 also gates the parity P1 for pulse t1 into a trigger contained in a Parity Storage Register.

At the time timing pulse t3 is produced, the Parity Generator output represents the parity of the Control Lines energized for pulses t1 and t2. To obtain and store the parity P2 for pulse t2 in the Parity Storage Register, the out...