Browse Prior Art Database

Logic Marginal Detector

IP.com Disclosure Number: IPCOM000097461D
Original Publication Date: 1962-Dec-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 37K

Publishing Venue

IBM

Related People

Ruehlman, JG: AUTHOR

Abstract

This circuit determines when a logical signal becomes ambiguous. A logic signal is defined as ambiguous when the operational devices cannot determine whether it is a logical 1 or logical 0.

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Logic Marginal Detector

This circuit determines when a logical signal becomes ambiguous. A logic signal is defined as ambiguous when the operational devices cannot determine whether it is a logical 1 or logical 0.

Two level detecting circuits are employed in parallel. Circuit No. 1 switches only when the minimum 1 level is exceeded. Circuit No. 2 switches only when the maximum 0 level is exceeded. The outputs from these level detecting circuits are fed to a comparator which switches when the outputs differ. Thus, only the ambiguous logic inputs that lie between the maximum 0 level and the minimum 1 level cause the comparator to switch.

Some benefits accrue from the fact that both level detectors employ the same type of components. Thus, degradation of the circuit parameters does not change the magnitude of the area of ambiguity.

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