Browse Prior Art Database

Memory Core Selection System

IP.com Disclosure Number: IPCOM000097471D
Original Publication Date: 1962-Dec-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Leightner, RA: AUTHOR [+2]

Abstract

In this memory array, only the address drivers along one coordinate provide bipolar current pulses.

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Memory Core Selection System

In this memory array, only the address drivers along one coordinate provide bipolar current pulses.

The four toroidal core memory elements are arranged for coincident current selection. This is in accordance with the energization of one X address conductor and one Y address conductor. Also, passing through each core is one sense winding and one inhibit winding.

Normally, when a selected core is to be energized for a reading operation, a current pulse is applied to the X address conductor passing through it. Another current pulse is applied to the Y current conductor also passing through it. Each pulse has a first polarity. On the other hand, during the writing operation in that selected core, the selected X address conductor and the selected Y address conductor each have a current pulse supplied to them having the other polarity. Meanwhile, the inhibit winding has a current pulse applied through it determined by whether or not a 1 or a 0 is stored in the selected core. Such magnetic memory matrix operation requires that the current drivers connected to both the X and Y address conductors be of a bipolar type. In addition, the inhibit driver need only be of the unipolar type.

The inhibit driver produces a current pulse which has the same polarity as the current pulses applied to the X and Y conductors during the reading operation. Thus, it is possible to use the inhibit driver and an address conductor along one of the coordinates (X or...