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Encoder and Decoder for Systematic Codes

IP.com Disclosure Number: IPCOM000097472D
Original Publication Date: 1962-Dec-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 88K

Publishing Venue

IBM

Related People

Hsiao, MY: AUTHOR

Abstract

A load sharing magnetic core matrix can be represented as a matrix of 1's and 0's. Each row represents a core and each column a winding. At the upper right there are illustrated diagrams of such a matrix. In this core circuitry, a load sharing matrix switch performs error detection and correction for systematic codes. Although any systematic code is applicable, a Hamming (7, 4) code suitable for single error correction is assumed for purposes of illustration.

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Encoder and Decoder for Systematic Codes

A load sharing magnetic core matrix can be represented as a matrix of 1's and 0's. Each row represents a core and each column a winding. At the upper right there are illustrated diagrams of such a matrix. In this core circuitry, a load sharing matrix switch performs error detection and correction for systematic codes. Although any systematic code is applicable, a Hamming (7, 4) code suitable for single error correction is assumed for purposes of illustration.

This matrix is for a Hamming (7, 4) code and the core winding matrix derived from it. Ones and 0's in the code matrix are equivalent to plus and minus 1's, respectively, in the winding matrix. Plus and minus 1's indicate oppositely wound turns in the core switch. Thus, the winding matrix can be imagined as a turns direction image of the switch windings, with each row corresponding to a switch core. The (7, 4) code implementation, therefore, comprises 16 switch cores (shown at the left) with seven complementary inputs (In for 1 and In for 0) comprising four information bits and three check bits.

In operation, a correct input code vector, for example, 0111001, applies maximum excitation to core 7. If I(d) is the output of a switch core, the correct output of core 7 is 1. For a single error, flux cancellation results in an output from the selected core of only 5 I(d). Since each driver delivers one-fifth of the current needed for switching, the correct core is still sele...