Browse Prior Art Database

Binary Buffer Storage Delay Lines

IP.com Disclosure Number: IPCOM000097477D
Original Publication Date: 1962-Dec-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 55K

Publishing Venue

IBM

Related People

Plonsky, AT: AUTHOR

Abstract

A system for time buffering digital information includes oscillators 11, 13 and 15 each providing a unique frequency. Binary digital information is entered via lines 17, 19 and 21 designated 2/0/, 2/1/ and 2/2/, respectively, to And's 23, 25 and 27. Depending on whether or not readout line 20 is energized, new data can be entered or the stored data recirculated. If flip-flop 29 is in its 0 state, indicating a time slot is available in the delay line output, the output on line 31 is combined with the write signal on line 33 in And 35, the output 37 of which conditions And's 23, 25 and 27. Those And's having a binary 1 input provide an output to condition And's 39, 41 and 43 through associated Or's 47, 49 and 51.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 78% of the total text.

Page 1 of 2

Binary Buffer Storage Delay Lines

A system for time buffering digital information includes oscillators 11, 13 and 15 each providing a unique frequency. Binary digital information is entered via lines 17, 19 and 21 designated 2/0/, 2/1/ and 2/2/, respectively, to And's 23, 25 and 27. Depending on whether or not readout line 20 is energized, new data can be entered or the stored data recirculated. If flip-flop 29 is in its 0 state, indicating a time slot is available in the delay line output, the output on line 31 is combined with the write signal on line 33 in And 35, the output 37 of which conditions And's 23, 25 and 27. Those And's having a binary 1 input provide an output to condition And's 39, 41 and 43 through associated Or's 47, 49 and 51. Assuming an input word 011, an output is provided from And's 23 and 25 which, in turn, produce a frequency coded output signal from And's 39 and 41. These signals are then combined in summing device 53. The output of 53 constitutes a signal having a waveshape and frequency corresponding to the sum of the component signals. After passing through delay line 55, access to the signals is obtained by filtering out the unique frequencies by filters 57, 59 and 61.

If recirculating is desired (no readout), the individual signals are applied through Or 63 to And 65. In response to the signal on line 67, the output from And 65 sets flip-flop 29 in the 1 state via gate 69, thus conditioning And's 71, 73 and 75. The second inputs to A...