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Browse Prior Art Database

Fully Checked Adder

IP.com Disclosure Number: IPCOM000097480D
Original Publication Date: 1962-Dec-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 28K

Publishing Venue

IBM

Related People

Sellers, FF: AUTHOR [+2]

Abstract

This binary full-adder, in generating an erroneous carry, also generates an erroneous sum. Thus, checking circuits used to detect errors in the sum also detect errors in the carry.

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Fully Checked Adder

This binary full-adder, in generating an erroneous carry, also generates an erroneous sum. Thus, checking circuits used to detect errors in the sum also detect errors in the carry.

Carry generator 20 delivers an output signal when two or three of the inputs A, B and C are present. The generator 20 output is used as one input to Exclusive Or 24 which generates the sum S. The output of function generator 22 is the other input to Exclusive Or 24. Generator 22 produces the function (A+B+C)* (bar A+bar B+bar C). It has Or 46 which responds to any one input. It also has And 52 which responds only when all inputs are present. The output of And 52 is inverted by 50 and fed to And 48 along with the output of Or 46. Thus, if there are one or two, but not three inputs, there is a function signal on line F.

With one input A, B or C, Exclusive Or 24 generates an output as, in this case, generator 22 delivers a signal and generator 20 does not. With two inputs, both 20 and 22 deliver an output, causing Exclusive Or 24 to indicate a zero. With three inputs only, generator 20 produces a signal, causing both outputs S and C' to be energized. If the carry is erroneous, the output of Exclusive Or 24 is reversed so that the sum is also erroneous.

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