Browse Prior Art Database

Pulse Monitoring and Correction

IP.com Disclosure Number: IPCOM000097481D
Original Publication Date: 1962-Dec-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 52K

Publishing Venue

IBM

Related People

Spenepser, DR: AUTHOR [+2]

Abstract

The circuit checks a pulse generator, such as a walking ring, for proper operation. The ring is periodically forced to assume a particular bit configuration when selected positions are in predetermined condition. An indication is also given when the ring fails to step altogether. The circuit insures that a correct ring status is established within a single cycle of operation.

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Pulse Monitoring and Correction

The circuit checks a pulse generator, such as a walking ring, for proper operation. The ring is periodically forced to assume a particular bit configuration when selected positions are in predetermined condition. An indication is also given when the ring fails to step altogether. The circuit insures that a correct ring status is established within a single cycle of operation.

The ring has seven positions and steps as indicated in the table. Ring clock position 1 2 3 4 5 6 7 1 reset 0 0 0 0 0 0 0 2 1 0 0 0 0 0 0 3 1 1 0 0 0 0 0 4 1 1 1 0 0 0 0 5 1 1 1 0 0 0 0 6 1 1 1 1 1 0 0 7 1 1 1 1 1 1 0 8 1 1 1 1 1 1 1 9 0 1 1 1 1 1 1 10 0 0 1 1 1 1 1 11 0 0 0 1 1 1 1 12 0 0 0 0 1 1 1 13 0 0 0 0 0 1 1 14 0 0 0 0 0 0 1

The ring clock positions 1... 7 are represented by upper and lower TV block pairs 1-2... 13-14, respectively. Stepping pulses from a high-speed oscillator 15 are applied to all ring positions in parallel through Sample Pulse Drivers (DSP) 16, 17 and 18. Outputs from block 1 and block 13 are applied to +And 21. When these positions are in a 1 state at step 8 of the above table, an output occurs from And 21. This is applied by line 22 to force positions 2...6 to also assume a 1 state. A particular ring bit configuration, 1 - 1 - 1 - 1 - 1 - 1 - 1, is thus established when a related subcombination, that is, 1's in positions 1 and 7, exists.

To check for a complete stopping failure, an output from oscillator 23 is periodically applied...