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Panel Meter Readout Turn-On Time Tester

IP.com Disclosure Number: IPCOM000097486D
Original Publication Date: 1962-Dec-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 37K

Publishing Venue

IBM

Related People

Millicker, DJ: AUTHOR [+2]

Abstract

This test circuit determines the turn-on and turn-off time parameters of a transistor under test. A positive pulse, produced by pulse generator 10, is applied to the base contact of socket 11, which, in this case, contains an NPN transistor. Likewise, the aforementioned pulse is applied to ramp generators 12 and 14. These then initiate the output of a pair of equal slope, linear, ramp voltages. As the leading edge of the positive input pulse at the base contact becomes more positive, the voltage at the collector of the transistor under test begins to fall. Any delay between these two phenomena is defined as the turn-on delay.

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Panel Meter Readout Turn-On Time Tester

This test circuit determines the turn-on and turn-off time parameters of a transistor under test. A positive pulse, produced by pulse generator 10, is applied to the base contact of socket 11, which, in this case, contains an NPN transistor. Likewise, the aforementioned pulse is applied to ramp generators 12 and 14. These then initiate the output of a pair of equal slope, linear, ramp voltages. As the leading edge of the positive input pulse at the base contact becomes more positive, the voltage at the collector of the transistor under test begins to fall.

Any delay between these two phenomena is defined as the turn-on delay.

The negative-going collector voltage output is coupled to the base electrodes of sense transistors 16 and 18. As the conduction of 16 and 18 decreases, their emitter voltages substantially follow the negativegoing collector voltage. Pick-off transistors 20 and 22 have their respective bases biased at the 10% and 90% switch voltage levels, delay and switch time, respectively. Thus, when the emitter circuits of transistors 16 and 18 reach the 10% and 90% levels, respectively, transistors 20 and 22 become conductive and collapse the ramps produced by generators 12 and 14. The peak voltages achieved by these ramps are detected and metered to provide indications of the delay and switch time for the particular transistor under test. The sensed delay and switch voltages are also subtracted from each other in differential amplifier 26 and provide an indication of the transition time, i. e., time between 10% and 90% voltage levels of...